The present invention relates to a data processor having an address translation mechanism and, more particularly, to a data processor having a set associative type cache memory used as the address translation mechanism. More particularly, the present invention is intended to diversify the address translation method and relates to a technique which is effective if applied to a microcomputer.
In the field where the operating system (as will also be referred to as the "OS") with the user being unconscious of the real memory, the data processor is required to support the address translation mechanism. This address translation mechanism is a mechanism for translating the logical address generated by the central processing unit (CPU) into a physical address so as to realize a virtual memory. In order to execute this address translation mechanism at a high speed, there is adopted a technique in which a translation lookaside buffer (as will also be shortly referred to as the "TLB") is packaged together with the central processing unit (CPU) in the data processor. The translation lookaside buffer is constructed, for example, as a buffer memory having an associative memory structure for latching a translation pair of the logical address and the physical address, which are recently used. The buffer memory having the associative memory structure can be exemplified by a full associative memory constructed of a CAM (i.e., Content Addressable Memory) having a comparing circuit construction in each memory cell, or a set associative memory capable of realizing a relatively high hit percentage by making use of a general purpose random access memory. Incidentally, the associative memory type translation lookaside buffer is disclosed, for example, on pp. 287 and 288 of "Super-High Speed MOS Device" issued by Kabushiki Gaisha Baifukan on Feb. 10, 1986.